The present invention relates to a solid state image sensing device comprising a number of static induction transistor cells arranged in a matrix form.
A solid state image sensing device having a number of cells arranged in a matrix form, each cell including a static induction transistor (hereinafter abbreviated as SIT) serving both as a photodetecting element and a switching element has been disclosed in a Japanese Patent Application Laid-open Publication No. 105,672/83.
FIG. 1A is a cross section illustrating an SIT forming a unit pixel of such a known solid state image sensing device and FIG. 1B is a circuit diagram showing a whole construction of such a solid state image sensing device. As shown in FIG. 1A, and SIT 1 comprises an n.sup.+ silicon substrate 1 constituting a drain, an n.sup.- silicon epitaxial layer 2 having a lower impurity concentration than that of the substrate 1, an n.sup.+ source region 3 and a p.sup.+ gate region 4, these regions 3 and 4 being formed by, for instance the thermal diffusion method. To the gate region 4 is applied an insulating film 5 made of, for example SiO.sub.2, and to the insulating film 5 is further applied a gate electrode 6. The gate region 4 constitutes a capacitance 7 together with the insulating film 5 and gate electrode 6. The gate electrode 6 is connected to a gate terminal 8. Adjacent SITs constituting the cells are isolated from each other by an isolation region 9 made of, for instance a burried insulating material. The n.sup.- epitaxial layer 2 constitutes a channel region of SIT. In the known solid state image sensing device, the SITs are formed as a normally-off type and thus, although the gate potential is zero volt, the channel region has been already depleted, so that even if a voltage is applied across the source and drain, a current does not flow between the source and drain.
In the known solid state image sensing device comprising the SITs of normally-off type, when a light input is given, hole-electron pairs are generated in the channel region 2 or the gate depletion layer. Electrons flow away into the drain, i.e. substrate 1 which is connected to the earth potential, but holes are stored in the signal storing gate region 4 and as the result of this the gate potential is increased by .DELTA.V.sub.G. Now it is assumed that the value of the gate capacitance 7 is C.sub.G and an amount of charge stored in the signal storing gate region 4 is Q.sub.L. Then .DELTA.V.sub.G =Q.sub.L /C.sub.G is obtained. After elapsing a certain signal storing time, when a gate readout pulse V.sub..phi.G is applied to the gate terminal 8, the gate potential becomes a sum of V.sub..phi.G and .DELTA.V.sub.G. Therefore, the potential between the signal storing gate region 4 and source region 3 is lowered and the depletion layer is decreased. Then a drain current corresponding to the light input flows between the source and drain. The drain current is proportional to .DELTA.V.sub.G increased by an amplification factor due to the amplifying function of SIT. It should be noted that the similar operation can be attained even if the source and drain of SIT are exchanged with each other.
FIG. 1B illustrates the circuit construction of the solid state image sensing device comprising the above explained SITs arranged in a matrix form. FIGS. 2A to 2D are signal waveforms for explaining the operation of the solid state image sensing device. SITs 10-11, 10-12 . . . are formed by n channel normally-off type SITs and an output video signal is readout in an XY address mode. A drain of an SIT constituting a pixel is connected to the earth potential. Sources of SITs arranged in rows, i.e. X direction are connected to row lines 11-1, 11-2 . . . , respectively which row lines are then connected commonly to a video line 13 via row selection transistors 12-1, 12-2 . . . , respectively. Further gate terminals of SITs arranged in columns, i.e. Y direction, are connected to column lines 14-1, 14-2 . . . , respectively. The video line 13 is connected via a load resistor 15 to a positive terminal of a D.C. voltage source 16 whose negative terminal is connected to the ground.
Next the operation for reading the output signals out of the pixels formed by SITs of the solid state image sensing device mentioned above will be explained. During a time interval in which a row selection pulse .phi..sub.S1 shown in FIG. 2A is applied to a transistor 12-1 connected to a row line 11-1 to turn on said transistor 12-1, when a gate readout pulse .phi..sub.G1 illustrated in FIG. 2C is applied to a column line 14-1, an SIT 10-11 is selected and a drain current of this SIT 10-11 flows through the load resistor 15 by means of the video line 13 to produce an output voltage V.sub.out at an output terminal 17. As explained above, the drain current is of a function of the gate potential which varies in accordance with the light input and thus an increment .DELTA.V.sub.out with respect to the voltage in the dark corresponds to the light input. In this case, the increment .DELTA.V.sub.out becomes a large voltage which is equal to .DELTA.V.sub.G multiplied by the amplification factor of the SIT. Next, a gate readout pulse .phi..sub.G2 shown in FIG. 2D is applied to a second column line 14-2 to readout SIT 10-12. In this manner all the SITs in the first column are successively readout. After that, a row selection pulse .phi..sub.S2 shown in FIG. 2B is applied to a second row selection transistor 12-2 to readout SITs in the second row. In this manner SITs of successive rows are readout sequentially.
The known solid state image sensing device explained above has been found to have the following disadvantages. When the gate readout pulse .phi..sub.G is applied to the gate region 4, a pn junction formed between the gate region 4 and drain is forwardly biased and therefore the holes stored in the gate region 4 flow away through the pn junction. In this manner, the light signals which have been stored in the gate regions of the SITs in a column line 14 are lost every time the gate readout pulse is applied to the relevant column line. Therefore, a light signal storing time in each pixel is determined by a ratio of the readout period with respect to the number of row lines and is equal substantially to a horizontal scanning period. In other words, it is assumed that the readout period is equal to T and the number of row lines is equal to n, then the light signal storing time is equal to T/n. Therefore, when the number of pixels is made large and thus the number of rows is increased, the storing time becomes extremely short and a light sensitivity is decreased. In this manner in the known solid state image sensing device it is practically impossible to derive a video signal having a high S/N.
Further in order to form the SIT as the normally-off type in the known solid state image sensing device, a distance W.sub.g between the inner edges of the gate region 4 has to be made very small. However, such a small distance could not be obtained easily in view of the manufacturing method.
Moreover, the normally-off type SIT has inherently a small current density and therefore, the signal current is very small.
As explained above, in the known solid state image sensing device, it is difficult to realize a useful device which can produce a large video signal and can be manufactured easily.